Abstract—The dynamically reconfigurable Field Programmable Gate Arrays (FPGAs) are most frequently employed for developing adaptive embedded systems. They are also being increasingly used as co-processors in high performance computing applications. For these systems to be fielded in harsh environments such as those encountered in space, extra- terrestrial locations and regions of extreme conditions on the earth, one must adopt fault tolerant design techniques to ensure uninterrupted and reliable operation despite the occurrence of faults. Commercial Off-the-Shelf (COTS) FPGA components offer a cost effective design trajectory where the designer can choose among a rich variety of FT approaches and techniques. This paper compares the various FT techniques and proposes a novel method in which these techniques can work together to provide a synergetic approach for fault tolerant FPGA design.
Index Terms—FPGA, fault tolerance techniques, dynamic partial reconfiguration.
Upasana Sharma was with the Division of Computer Engineering, Netaji Subhas Institute of Technology, New Delhi, India -110078. She is now with Safenet Inc., Noida, (U.P.), India - 201301 (e-mail: upasanash@yahoo.com).
Shampa Chakraverty is with the Division of Computer Engineering, Netaji Subhas Institute of Technology, New Delhi, India - 110078 (e-mail: apmahs@gmail.com).
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Cite: Upasana Sharma and Shampa Chakraverty, "A Novel Approach for Providing Fault Tolerance to FPGA-Based Reconfigurable Systems,"
International Journal of Engineering and Technology vol. 4, no. 6, pp. 821-825, 2012.
