Abstract—In the past decades CMOS IC technologies have been constantly scaled down and at present they aggressively entered in the nanometer regime. Amongst the wide-ranging variety of circuit applications, integrated memories especially the SRAM cell layout has been significantly reduced. As it is very well know the reduction of size of CMOS involves an increase in physical parameters variation, this is a factor which has a direct impact on SRAM cell stability. Polysilicon and diffusion critical dimensions (CD) together with implant variations are the main causes of mismatch in SRAM cells. SRAM memory cells have always been designed to occupy the minimum amount of silicon area consistent with the performance and reliability required. Today’s system on Chip (SoC) trends result in a major percentage of the total die area being dedicated to memory blocks, consequently making SRAM parameter variations dominate the overall circuit parameter characteristics, including leakage, process variation effects, etc. The reliability is usually measured by static noise margin, SNM [1], and write trip point simulations and measurements. In this paper we have analyzed the stability of the 9T SRAM cell at SS, FF, TT, FS, SF corners. The simulations have been done at 45nm technology.
Index Terms—SOCs, Embedded SRAM, Scaling, Deep submicron level.
R. K. Singh is with BTKIT, Uttarakhand, India.
Shilpi Birla is with SPSU, Udaipur, India. (Email: shilpibirla@gmail.com)
Manisha Pattanaik is with ABV-IIITM Gwalior, India.
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Cite: R. K. Singh, Shilpi Birla, Member, IACSIT, and Manisha Pattanaik, "Characterization of 9T SRAM Cell at Various Process Corners at Deep Sub-micron Technology for Multimedia Applications," International Journal of Engineering and Technology vol. 3, no. 6, pp. 696-700, 2011.
