Abstract—Scaling the minimum feature size of VLSI circuits to sub-quarter micron and its clock frequency to 3GHz has caused crosstalk noise to become a serious problem that degrades the performance and reliability of high speed integrated circuits. This paper presents an efficient method for computing the capacitive crosstalk in sub-quarter micron VLSI circuits. In this paper, we present a complete analytical crosstalk noise model which incorporates all physical properties including victim and aggressor drivers, distributed RC characteristics of interconnects and coupling locations in both victim and aggressor lines. We present closed-form analytical expressions for peak noise and noise width to estimate on-chip crosstalk noise and also shown that crosstalk can be minimized by wire spacing and wire sizing optimization technique. These models are verified for various deep submicron technologies.
Index Terms—Aggressor, Coupling, Crosstalk, Interconnect noise, Wire spacing.
P. V. Hunagund is with the Department of Applied Electronics, Gulbarga University, Gulbarga, India (e-mail:prabhakar.hunagund@gmail.com).
A. B. Kalpana is with the Electronics and Communication Engineering Department, Bangalore Institute of Technology, Bangalore, India (e-mail: abkalpana@gmail.com).
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Cite: P. V. Hunagund and A. B. Kalpana, "Crosstalk Interconnect Noise Optimization Technique Using Wire Spacing and Sizing for High Speed Integrated Circuits," International Journal of Engineering and Technology vol. 3, no. 6, pp. 684-688, 2011.
