Abstract—For mobile and multimedia applications of SRAMs, there is a strong need to reduce standby current leakages while keeping the memory cell data unchanged. To meet this objective, various techniques have been developed to reduce the leakage current at the process/device, circuit, architecture, and algorithmic levels. The traditional 6T CMOS SRAMs face many challenges in deep-submicron (DSM) technologies for low supply voltage (VDD) operation. Predictions suggests that process variations will limit standard 90nm SRAMs to around 0.7V operation because of the Static Noise Margin (SNM) degradation and write margin, also a VDD of 0.7V is reported for a 65nm SRAM. This work discusses some of the schemes that minimizes the cell leakage regardless of the process fluctuations and the environmental conditions. Various SRAM leakage currents identifies the suitable schemes for 6T SRAM sub-threshold operation at device and circuit levels for optimal sub-threshold circuit designs and provides an effective roadmap for digital circuit designers who are interested to work with ultra-low-power applications in CMOS technology.
Index Terms—DSM (Deep Sub-Micron), Power Gating, SNM (Static Noise Margin), Sub-threshold Operation, Data Retention.
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Cite: Neeraj Kr. Shukla, Shilpi Birla, R.K. Singh and Manisha Pattanaik, "Analysis of the Effects of the Operating Temperature at the Performance and Leakage Power Consumption in a Conventional CMOS 6T-SRAM Bit-Cell at 65nm, 45nm, and 32nm Technologies,"
International Journal of Engineering and Technology vol. 3, no. 1, pp. 1-8, 2011.
